Field of Invention
The present invention relates to an iterative decoding device, an iterative signal detection device, and an information update method for the same, and in particular to, an iterative decoding device which is applied for a SISO (soft input soft output) system.
Description of Prior Art
Nowadays, in the field of wireless communication systems, a transmitter will encode source information, the coded source information might be interfered by channel during a transmission process. However, it is possible to correct the error, finitely. In order to increase the data rate and the reliability, a MIMO (multi-input multi-output) system is used to transmit the above source information. However, in a relative receiver, each antenna will receive the source information and also be influenced by channel noise and other source information transmitted from other antennas.
Please refer to FIG. 1, which is a functional block diagram of a prior SISO systematic architecture, which comprises a conventional receiver. When the receiver receives the coded source information, a detector 11 therein the conventional receiver to interpret the source information transmitted by each of antennas, then the source information is inputted into a decoder 12 in turns; however, the detector 11 only transmits the soft-information to the decoder 12 by one way. There is no soft-information exchange between the detector 11 and the decoder 12 such that the system is unable to effectively use the soft-information to raise the system performance.
Please refer to FIG. 2, which is an information processing timing diagram of another prior SISO systematic architecture having differences from the architecture illustrated in FIG. 1 in that: the detector 11 is replaced by a first decoder and the decoder is replaced by a second decoder, in order to make the first decoder and the second decoder both functioning on soft-information exchange therebetween. However, an issue is found in FIG. 2 that although the soft-information exchange can be performed between the first decoder and the second decoder, the first decoder and the second decoder only can sequentially process one frame for each cycle period; namely, while the first decoder is processing a frame 1, the second decoder is idle; and then after the first decoder transmits the processed frame 1 to the second decoder for further operation, the first decoder is idle. In this manner, the operational speed of the system hardware is not only slowed but also the usage efficiency of the system hardware is lowered.